1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, more particularly to a semiconductor integrated circuit device having a circuit used for delay adjustments.
2. Description of Related Art
When designing a DDR (Double Data Rate) system or the like, both rising and falling edges of signals are used. In case of such a DDR system, however, when the signal waveform duty ratio is deviated from 50%, it is becoming difficult more and more to keep the setup time and hold time, for example, in the input side flip-flop process or the like. In case of a system used for fast clock transmissions, if the signal waveform duty ratio is deviated from 50%, then the eye aperture rate falls, thereby the number of errors that might occur at the receiving side comes to increase. Consequently, such a system is usually required to have a function for adjusting the output signal duty ratio so as to be fixed at 50%.
The patent document 1 discloses a semiconductor integrated circuit device, which includes an output buffer circuit. The output buffer circuit includes a pull-up circuit and a pull-down circuit. The pull-up circuit supplies a charging current to an output terminal to pull up the potential level and the pull-down circuit pulls out the discharging current from the output terminal to pull down the potential level. In case of this semiconductor integrated circuit device, at least one or more resistors are connected to each another serially either between an output end and an output terminal of the pull-up circuit or between an output end and an output terminal of the pull-down circuit. In each of those resistors, both ends thereof are short-circuited or opened. In such a semiconductor integrated circuit device, the signal waveform duty ratio can be adjusted by adjusting each of the rising and falling waveforms independently even when the driving performance is unbalanced between rising and falling edges of signals, thereby the digital signal waveform duty ratio is unbalanced.
The patent document 2 discloses a layout for quickening the operation of a standard cell in a specific transient direction without changing its height. This layout can lower the threshold voltage of either the pMOS transistor or the nMOS transistor among the transistors of the cell, thereby quickening the operation of the standard cell in a specific transient direction without changing its shape. For example, in order to lower the threshold voltage of the nMOS transistor, the layout can change the amount of impurity ions to be implanted in the channel region of the nMOS transistor.
The patent document 2 also discloses a similar layout that can quicken the operation of an object standard cell only in one transient direction by changing and matching the well boundaries at both ends of the cell only with respect to the transistors in the cell while keeping the height of the standard cell. If it is impossible to change the threshold voltage only in the pMOS or NMOS transistor, for example, even when the threshold voltages of both NMOS and pMOS transistors are lowered up to their limits, then the layout enables the operation of the standard cell to be quickened in a specific transient direction while keeping the height, although the width of the cell comes to increase by several to several tens of percentage.
[Patent document 1] Japanese Patent Application Laid Open No. Hei5(1993)-102826
[Patent document 2] Japanese Patent Application Laid Open No. 2003-330984